1. Field of the Invention
This invention generally relates to a chip package structure, and more particularly to a chip package structure including a glass substrate.
2. Description of the Related Art
Flip chip technology is widely used for chip packaging. Flip Chip describes the method of electrically and mechanically connecting the die to the package carrier. The package carrier then provides the connection from the die to the exterior of the package. The interconnection between die and carrier in flip chip packaging is made through a conductive bump that is placed directly on the die surface. The bumped die is then flipped over and placed face down, with the bumps electrically and mechanically connecting to the carrier. After the die is mounted, an insulated material is applied between the die and the substrate, around the solder bumps. The insulated material is designed to buffer the stress in the solder joints caused by the difference in thermal expansion between the silicon die and carrier.
The boom in flip chip packaging results both from flip chip's advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widely available flip chip materials, equipment, and services. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Hence, Flip chip technology is suitable for high pin count package. Some of well-known applications of flip chip technology are flip chip ball grid array (“FC/BGA”) and flip chip pin grid array (“FC/PGA”).
FIG. 1 is the cross-sectional view of a conventional FC/BGA chip package structure. The chip package structure 100 includes a substrate 110, a die 130, and a plurality of bumps 140 and balls 150. The substrate 110 includes a top side 112, bottom side 114, and a plurality of bump pads 116a and ball pads 116b. The die 130 includes an active surface 132 and a corresponding back side 134. The die 130 also has a plurality of die pads 136 on the active surface 132 for the signal outputs of the die 130, wherein the positions of the bump pads 116a correspond to those of the die pads 136 respectively. The bumps 140 electrically and mechanically connect the bump pads 116a to the die pads 136. The balls 150 are set on the ball pads 116b to electrically and mechanically connect to external circuits.
Referring to FIG. 1, the insulated material 160 is applied between the top side 112 of the substrate 110 and the active surface 132 of the die 130 to protect the exposed portion of the bump pads 116a, the die pads 136 and bumps 140. The insulated material 160 is designed to buffer the stress in the solder joints caused by the difference in thermal expansion between the die 130 and the substrate 110. Hence, the die pads 136 are electrically and mechanically connected to the bump pads 116a via the bumps 140, and are coupled to the ball pads 116b via the wiring inside the substrate 110. Then the balls 150 on the ball pads 116b electrically and mechanically connect to external circuits.
To reduce the production costs and enhance the operation speed, the size of the die and the pitch between the die pads are getting smaller. Hence, the density of the die pads becomes higher. When FC/BGA or FC/PGA technology is applied to a die having high die pad density, a substrate having a high-density layout is required. The well-known dielectric materials of substrates for FC/BGA or FC/PGA include ceramic or organic materials, wherein the organic substrates are the most common substrates. Because of the process limitation of organic substrates, the critical dimensions of the line width and pitch are both 25 μm for the existing organic substrates. Because it is difficult to increase the bonding pad density on the existing organic substrates, when the density of the die pads becomes higher, the existing organic substrates could not meet the requirement of high bonding pad density.